1. The XAUI IP core is designed to the standard specified in clauses 47 and 48 of the 10 Gigabit Ethernet specification IEEE Std. The MAC core along with FIFO-core and SPI4/AXI-DMA engines VMDS-10298. 10GBASE-KR is an Ethernet defined interface intended to enable 10. The IEEE 802. Received Ethernet bytes are available on the 64-bit XGMII interface (RX_MII_D/C). 3125 Gbps serial line rate with 64B/66B encoding 10GBASE-KR and 1000BASE-KX is the electrical backplane physical layer implementation for the 10 Gigabit and 1 Gigabit Ethernet link defined in clause 72 and clause 70. The modules are capable of operating with XGMII interface widths of 32 or 64 bits. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. 25MHz. DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). 1. 0 > 2. Transceiver Status and Reconfiguration Signals 6. Xilinx also has 40G/50G Ethernet Subsystem IP core. 3-2008 specification. Getting Started x 3. • Operate in both half and full duplex and at all port speeds. XGMII interface in my view will be short lived. Features 6. Each comma is. XAUI addresses several physical limitations of the XGMII. 2 specification supports up to 256 channels per link. It can also be used as a serial communication bus between the PowerQUICC™ MPC8313E and other peripherals such as through a. The Gigabit-Ethernet media independent interface (GMII) specified by IEEE802. 1. This project will specify additions to and appropriate modifications of IEEE Std 802. – Make MDIO/MDC part of each optional interface (XGMII, XAUI, XSBI, SUPI) • Any device with one of these interfaces would have to also implement MDIO/MDCIEEE 1588v2 Timestamp Interface Signals 7. I see three alternatives that would allow us to go forward to > TF ballot. For Ethernet backplane applications, XGMII compliant 10GBASEKR_PHY soft IP is developed. 25MHz for direct interface to 10GBase-R, XAUI and RXUAI cores. 2 V or 2. 4. (MAC), PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T PHY standard devices. For more information on aggregation mode, refer to the C-5 Network Processor Architecture Guide. 3125 Gb/s. Application. 2023年11月1日 閲覧。 ^ “QSGMII Specification” (2009年7月20日). 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Updated for Intel ® Quartus Prime Design Suite: 19. Check Link Fault status signal, value 01 (Local Fault). The XGMII interface, specified by IEEE 802. RGMII to GMII converter provides the interface between a standard gigabit media independent interface (GMII) to RGMII conversion. 2. 75 Gbps raw data trans-mission capacity. 1. It also supports the 4-bit wide MII interface as defined in the IEEE 802. Performance and Resource. Core data width is the width of the data path connected to the USXGMII IP. 1 Voltage Mode Line DriverCollection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). 3 that describe these levels allow voltages well above 5V, but I don't know of any 1. 14. 802. This interface specification is subject to modification and revision to incorporate changes, improvements, and enhancements. Rockchip RK3588 datasheet. 5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core implements USXGMII PCS based on Cisco specification. In other words, you can say that interfaces can have abstract methods and variables. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including: Definitely not XGMII (32-bit DDR, was never really seen off-chip) or XAUI (4 lanes of 3. The IEEE 802. It's an attempt to realize the Open RAN concept. The primary. 3 are described in terms of two primary interfaces Medium dependent interface (MDI) Media independent interface (MII) While the MDI is visible to the user, and usually tightly specified, the MII is often used simply as a convenient way to partition the physical layer specifications from the10 ギガビット イーサネット PCS/PMA (10GBASE-R) は、10 ギガビット イーサネット MAC への接続に XGMII インターフェイスを提供し、10. 25 Gbps) implementations on Stratix IV (GX and GT) FPGAs. MAC – PHY XLGMII or CGMII Interface. 4. There are a total of 28 pins within a cluster, so each cluster has enough signals to implement one GMII interface. 25GMII is similiar to XGMII. Each (MAC) with a XGMII (10 Gigabit Media Independent Interface) for incorporation in a customer’s ASIC design. The Reduced Gigabit Media Independent Interface (RGMII) module provides an RGMII interface to an existing Ethernet MAC design with a GMII or TBI interface, for example the Gigabit Ethernet MAC (GEM) available from Cadence Design Foundry. For D1. Release Information 2. interface is the XGMII that is defined in Clause 46. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. License: LGPL. The _DSD object is a device specific configuration object, intended for firmware and software engineers implementing _DSD or designing. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification. 18-199x Revision 2. 5G, 5G, or 10GE data rates over a 10. 2) enabled TX and RX bit in TX_ctrl and Rxctrl registers . XGMII Signals Signal Name Direction Width. The original single row of pins is compatible. It can be replaced by a resistor-capacitor combination, both of package size 0603. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. The XgmiiSink receives XGMII traffic, including monitoring internal interfaces. Timing wise, the clock frequency could be multiplied by a factor of 10. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. 3 standard. 2 XAPP606 (v1. It also supports the 4-bit wide MII interface as defined in the IEEE 802. Leverages DDR I/O primitives for the optional XGMII interface. 1 XGMII Interface The XGMII interface connects the Reconciliation Sublayer (RS) with the IP and allows transferring information to/from as defined in Clause 46. 2. It is called XSBI (10 Gigabit Sixteen Bit Interface). Xilinx has 10G/25G Ethernet Subsystem IP core. 3z specification. Section Content Features Release Information LL. In computer networking, Gigabit Ethernet ( GbE or 1 GigE) is the term applied to transmitting Ethernet frames at a rate of a gigabit per second. It differs from GMII by its low-power and low pin count serial interface (commonly referred to as a SerDes ). PLS. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. 3ae specification, the 10Gb Ethernet MAC (10 GMAC) core includes the option of either a parallel 10 Gigabit Media Independent Interface (XGMII) or a serial 10 Gigabit Attachment Unit Interface (XAUI). A DLLP packet starts with an SDP (Start of DLLP Packet -. 8. 25 MHz • Same clock domain for transmit and. September 23, 2021 Product Specification Rev1. The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 10M, 100M, 1G, 2. Core data width is the width of the data path connected to the USXGMII IP. Lane 0 data: xgmii_tx[7:0] Lane 0 control: xgmii_tx[8] Lane 1 data: xgmii_tx&lbrack. 4)checked Jumper state. 25 MHz interface clock. OpenCores 10GE MAC Core Specification 1/19/2013 RX Enqueue Engine In the RX Enqueue Engine, the RC layer monitors the XGMII interface for fault conditions and pass the status to the Fault State-Machine. This block contains the signals TXD (64. normal signal, the XGMII input is ignored until PCS_Test. 802. With experience of SSTL, I believe we can define the HSTL interface in more reasonable time frame. Close Filter Modal. The satellite manufacturer, Lockheed Martin, compiled the information based on its design specifications and ground test measurements of the antenna panels. 8. USGMII Specification. In this document, the term “GMII” covers all 10/100/1000 Mbit/s interface operations. So to test initially I taken Example design of PCS/PMA IP and there I altered 1) ctl_loopback bit 1-> 0 (not setting in loop back) . XFI和SFI的来源. 4. That being said, there may be an assumption made that a 10 Gb/s MAC/RS/XGMII implementationSerdes Lane A is connected to a Broadcom Ethernet switch on the board via SGMII. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-610010Gb Ethernet Core Designed to the Draft 4. 3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA. 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. and added specification for 10/100 MII operation. Network Management. 1. I see three alternatives that would allow us to go forward to > TF ballot. 4)checked Jumper state. conversion between XGMII and 2. ANSI TR/X3. As a result the above text only applies to XGMII 10 Gb/s operation and IEEE 802. Inter-Frame GAP - Deficit Idle Count per Clause 46 3. You are required to use an external PHY device to. Use Case ‘Front Light Management’: Exchange Type of Front Light. I would not want to retain the current electrical specification. SerDes TX RX MII SerialThis solution is designed to the IEEE 802. Each channel operates from 1. 1. 0 > 2. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. 6. 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. The names, trademarks and file systems used are listed in Table 1 (below). 8. X20473-0306. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture 6. 5GPII Implementation as shown does not require much incremental logic Does not preclude implementations that directly map XGMII into PCS Diagram above for IEEE functional specification purposes only 1000BASE-X PHY 2. 4. Small Form-factor Pluggable connected to a pair of fiber-optic cables. Loading Application. Uses two transceivers at 6. The RGMII interface has been designed in accordance with the standards and specifications agreed in theThe CoaXPress-over-Fiber Bridge IP Core allows to connect a CoaXPress IP Core to an XGMII (10 Gbps Media Independent Interface) bus inside an FPGA. These published antenna patterns and associated Institute of. Xilinx also has 40G/50G Ethernet Subsystem IP core. XAUI uses four full-duplex serial links operating at 3. The code-group synchronization is achieved upon th e reception of four /K28. e. The Full-Speed SDIO devices have a data transfer rate of over 100 Mb/second (10 MB/Sec). Operating Speed and Status Signals The XAUI PHY uses the XGMII interface to connect to the IEEE802. Reference HSTL at 1. The interface between the PCS and the RS is the XGMII as specified in Clause 46. キーワード : 606, XAPP, broken link, application, note, XGMII, リンク切れ, アプリケーション, ノート サイトに、アプリケーション ノート (XAPP606)、『10-Gigabit Media Independent Interface (XGMII) Reference Design』の記述やリンクがありますが、文書が見つからず、リンクも壊れています。The present clauses in 802. > > 1. Both jobs do a lot of work, and have to know a lot. It utilizes built-in transceivers to implement the XAUI protocol in a single device. NVMe-MI technology provides an industry standard for management of NVMe devices in-band. . N GMII Electrical Specification Page 8 IEEE P802. Reconfiguration Signals 6. 5G、5G、または 10GE のシングル ポートを使用するメカニズムを持つ Ethernet Media Access Controller (MAC) を実装します。(1) The reconciliation sublayer (RS) interfaces the serial MAC data stream and the parallel data of XGMII. Configuration Registers x. 6. 3125 Gbps のシリアル シングル チャネルの PHY をインプリメントして、XFI 電気的仕様を使用した XFP への直接接続や、SFI 電気的仕様を使用した SFP+ オプティカル. 6. 25 Mbps. 5 Gb/s and 5 Gb/s XGMII operation. 1G/2. As I have pointed out in prior notes, a prevalent XAUI application will be as a fixed chip-to-chip interconnect not involving optical modules at all. Media Independent Interface ( MII )，介质独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. Features 2. 8. The Full-Speed card supports SPI, 1-bit SD and the 4-bit SD transfer modes at the full cloc k range of 0-25MHz. In contrast, the XLGMII/CGMII interfaces are intended only for use on-chip, and are defined differently as SDR interfaces, see 802. USXGMII (Universal Serial 10GE Media Independent Interface) IP コアは、IEEE 802. 3125 Gbps serial single channel PHY over a backplane. Loading Application. More details are provided in Chapter3, Designing with the Core. • No internal interface is super-rated, • XGMII rate is preserved (312. Media-Independent Interface（MII、媒体独立インタフェース）は、イーサネットにおいて、MAC (データリンク層デバイス)とPHY (物理層デバイス)とを接続するためのインタフェース。本稿では以下の拡張版を含めて記述する。 The XGMII interface defines the 32-bit data and 4-bit wide control character clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156. Field Name Type Description; openapi: string: REQUIRED. 5. ECU-Hardware. We are using the Yocto Linux SDK. 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto. 2) enabled TX and RX bit in TX_ctrl and Rxctrl registers . Status Signals. These characters are clocked between the MAC/RS and the PCS at both the positive and negative edge (double datarate – DDR) of the 156. Figure 49–4 depicts the relationship and mapping interface. Register Interface Signals 5. . 1 R2. The IEEE 802. XGMII. The PCS service interface is the XGMII, which is defined in Clause 46 running at 5Gb/s. 4. ‡ þÿÿÿ ‚ ƒ. 1. 1 Overview This clause defines the logical and electrical characteristics for the Reconciliation Sublayer (RS) and 10Gigabit Media Independent Interface (XGMII) between Ethernet media access controllers and various PHYs. Reference HSTL at 1. 2. The XgmiiSource and XgmiiSink classes can be used to drive, receive, and monitor XGMII traffic. to the PCS synchronization specification. TOD Interface Signals. 5. So I don't think there's an easy way to connect 100G and 25G. 3 protocol and MAC specification to an operating speedof 10 Gb/s. 1858. 3ae-2002 specification requires the XAUI PHY link to support a 10 Gbps data rate at the XGMII interface and four lanes each at 3. 4. 1. 7. 3125Gbps transmission across lossy backplanes. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. Includes MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination. Interface XGMII/ GMII/MII External PHY Serial Interface. Designed to Dune Networks RXAUI specification. At the Tampa meeting I intend to propose that we just adopt the logic family that the XGMII uses (we might have to put a note in about termination schemes as the MDIO is multi-drop). Standardized. The 5GBASE-R PCS provides all services required by the XGMII including Encoding (decoding) of XGMII data octets to (from) 64B/66B blocks for communication with the underlying PMA. The BCM84885 supports the USXGMII, XFI, 5000BASE-X, 2500BASE-X, and 1000BASE-X (SGMII) interface for connection to a MAC. 5x faster (modified) 2. On the user side a pair of AXI4-Stream (one master and one slave) interfaces are used to send and receive Ethernet frames from/to the user logic. The XAUI interface is short, the laser driver to XAUI interface is likely to be custom, and DC-coupling is appropriate. Table 1. 5V tolerance seems an unnecessary burden. Introduction. The PCS IP is engineered to be quickly and easily integrated into any SoC, and to connect seamlessly to a Cadence or third-party MAC through a demultiplexed XGMII (64-bit data, 8-bit control, single clock-edge interface). There needs to be some way to allow alternate voltages for this interface and still be standards compliant. 2 Performance 10 2. As far as I understand, of those 72 pins, only 64 are actually data, the remai. This is a 64-bit bus that runs at 156 MHz for 10 Gbps or up to 187. These specs were defined by the SFF MSA industry group. This revision offers architecture diagram of Non-RT RIC, collects requirements on the Non-RT RIC framework, Non-RT RIC logical functions and services of the R1 interface. Configuration Registers A. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP\+ optical module using SFI electrical specification. 1. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of. The 10 Gigabit Ethernet PCS/PMA (10GBASE-R) is a no charge LogiCORE™ which provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10. Return to the SSTL specifications of Draft 1. L- and H-Tile Transceiver PHY User Guide. XGMII Signals 6. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. For D1. When TCP/IP network is applied in. 4. Same thing applies to TXC. Transceiver Status and Reconfiguration Signals 6. Avalon® Memory-Mapped Interface Signals 6. 3-2008 specification. 3ae-2002 standard. Table of Contents IPUG115_1. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User GuideIP is needed to interface the Transceiver with the XGMII compliant MAC. Thanks, I have this problem too. // Documentation Portal . Medium. I see three alternatives that would allow us to go forward to > TF ballot. . (MAC) core, which can be configured in XGMII and 10GBASE-R modes. XGMII Ethernet Verification IP. 8. GMII- Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a 1000 Mbit/s PHY and a MAC sublayer. The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. Front-Light Manager. In order to connect a 10-Gigabit Ethernet MAC to an off-chip PHY device, an XGMII inter-face is used. Device Speed Grade Support 2. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Lane 0: xgmii_tx_control[0] Lane 1: xgmii_tx_control[1] Lane 2: xgmii_tx_control[2] Lane 3: xgmii_tx. PHY /Link interface specification , . 6 GHz and 4x Cortex-A55. 49. Supports 10M, 100M, 1G, 2. The XGMII Controller interface block interfaces with the Data rate adaptation block. Each comma is. 3125 Gb/s link. The signal BD_SEL# is tied to GND by a removable copper link. The IP core is compatible with the RGMII specification v2. Introduction. The objectives of the five workstreams are the following: M-HPM (Host Processor Modules) Workstream which involves three specifications: M-FLW (FulL Width HPM) Specify the requirements of a Full Width Host Processor Module (HPM). Network. 3 Fibre Channel - 10-bit Interface Specification. - XGMII Interface (64-bit single clock edge) - POS-L3 like Interface for core logic side. 5000BASE-X, 2500BASE-X, and 1000BASE-X (SGMII) interface for connection to a MAC. 125Gbps 10GBASE-R Clause 49 (IEEE 64B/66B PCS only) o No IEEE Electrical Spec (no PMA) IEEE Specifications • 3. After that, the IP asserts. 1. 0 > 2. 3. This is the ACPI _DSD Implementation Guide. the 10 Gigabit Media Independent Interface (XGMII). Statement on Forced Labor. 1 XGMII Controller Interface 3. Therefore, it is necessary to complete the conversion of GMII to XGMII interface in firmware. In each table, each row describes a test case. Ethernet Verification IP is developed by experts in Ethernet, who have developed ethernet. 本文非原创，摘自：Media Independent Interface Media Independent Interface ( MII)，媒体独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. 25 Gbps. XGMIIはMACとPHYの間に位置する。RSはMACのビットシリアルプロトコルをPHYのパラレルエンコーディングに適合させる。 XGMIIの使用は必須ではないが、PCSはXGMIIを想定して仕様が定義されて. 3 media access control (MAC) and reconciliation sublayer (RS). XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between. It is now typically used for on-chip connections. 1. 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Interfaces. XGMII Update Page 12 of 12 hmf 11-July-2000 IEEE 802. 3az standard for Energy Efficient Ethernet. 2023年11月1日 閲覧。 ^ IEEE 802. xgmii mdi up to 10 gbps clt – coax line terminal cnu – coax network unit mdi – medium dependent interface oam – operations, administration, & maintenance pcs – physical coding sublayer phy – physical layer device pma – physical medium attachment pmd – physical medium dependent xgmii – gigabit media independent interfaceManagement Data Input/Output (MDIO) interface Clause 46. This specification defines USGMII. 10 GIGABIT ETHERNET SGMII supports a single 10M/100M/1G network port over 1,25Gbps SERDES between MAC and PHY, while QSGMII supports four 10M/100M/1G network ports over 5Gbps SERDES between MAC and PHY. 5G, 5G, and 10G. arm is only willing to license the relevant amba specification to you on condition that you accept all of the terms in this licence. specification for internal use only. Reconfiguration Signals 6. f) Modified Intellectual Property statement to address incorporation of IP from multiple sources. 3-2018, Clause 46. 25 MHz interface clock. com N. This specification supports longwave (wavelength is 1310 nanometers) Single-Mode Fiber (SMF) whose. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. XGMIIはMACとPHYの間に位置する。RSはMACのビットシリアルプロトコルをPHYのパラレルエンコーディングに適合させる。 XGMIIの使用は必須ではないが、PCSはXGMIIを想定して仕様が定義されて. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. 5Gb/s 8B/10B encoded - 3. 10G/2. : info: Info Object: REQUIRED. com Features See Reference Design Manual • 10 Gbps Ethernet • 10G PHY interface: 64-bit XGMII interface at 156. The host layer access to the Controller IP for Automotive is through industry-standard AXI or AHB interfaces when the DMA is being used or through an external FIFO interface. 3u）。介质独立的意思是指，MAC与PHY之间的通信不受具体传输介质（双绞线或光纤等）的影响，任何MAC和PHY都可以通过MII接口互连。 MAC与PHY之间的MII连接可以是可插拔的连… Interface Avalon-ST XGMII/ GMII/MII 10M/100M/ LL 10GbE MAC PHY Serial Interface Note: Intel FPGAs implement and support the LL 10GbE Media Access Control (MAC) and Multi-Rate Ethernet PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T (1G/2. -Avalon ST TX and RX input/output signals to Avalon ST TX/RX 64 bit adapter. 11. Unidirectional. You may refer to the applicable IEEE802. 6 Functional block diagramHow is data transferred from the XAUI to the User interface? A8. 7. PCS. The PHY we have on the LS1046A RDB supports native XFI but sends PAUSE frames towards the MAC to regulate the lower speeds. This is not related to the API info. The XGMII Controller interface block interfaces with the Data rate adaptation block. 11/13/2007 IEEE 802. XFP光模块标准定义于2002年左右，其内部的收和发方向都带有CDR电路。. I would like to get some clarification for the " Universal SXGMII Interface for a Single MultiGigabit Copper Network Port" specification. 4. I also believe that backwards compatibility is a good thing. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. What i want to do is i want to feed the PCS with xgmii_tx signals, connect the txn/txp to rxn/rxp respectively and monitor the xgmii_rx signals whether they are the same as xgmii_tx. 25 Gbps. Interface (XGMII) to the protocol device. XAUI interoperability is based on the 10-Gigabit Ethernet standard (IEEE Standard 802. 3 standard. TXC<3:0> and RXC<3:0> are the data delimiters for these four byte lanes and separate frame data bytes from controlThe limitation on the clock speed was due to the capacitive load associated with having 32 bi-directional pins on an MDIO bus. Table 1. Each direction is independent and contains a 32-bit. Core10GMAC supports standard Ethernet interfaces such as the 10 Gbps attachment unit interface (XAUI) and the 10 Gbps reduced attachment unit interface (RXAUI). The switch is capable of auto-negotiating with SGMII and 1000BaseX connections and by default set to SGMII. 1 Online Version Send Feedback UG-20071 ID: 683876 Version: 2021. 1. 5G/5G/10G Multi-rate PHY. Want to thank TFD for its existence? Tell a friend about us, add a link to this page, or visit the webmaster's page for free fun content. Introduction.